Projects

Yaseen built a real-time matched-filter object detector on the Terasic DE1-SoC using a D8M camera input and VGA output. Its Verilog pipeline combines streaming line buffers, matched-filter cores, and hardware cross-correlation against custom template weights generated in Python. VGA debug modes show heatmaps, threshold masks, bounding boxes, and confidence scores; testbenches verify feature extraction, stream delays, scoring, and detection logic.

Yaseen designed a compact, synthesizable RV32I-style RISC-V core implemented in Verilog. It includes a program counter, register file, ALU, control unit, and synchronous instruction/data memories targeting Intel M9K BRAMs. He verified functionality with Verilog and C/C++ testbenches in ModelSim and Verilator, then used OpenLane for ASIC synthesis, floorplanning, placement, clock-tree synthesis, routing, and timing closure through GDS II generation.

Yaseen implemented a minimal but functional RISC-V RV32 microkernel that boots in machine mode on QEMU's virt platform. The kernel includes hand-written entry and trap assembly, timer interrupts, context switching, kernel threads with dedicated stacks, and semaphore-based synchronization. Written in C and RISC-V assembly, it uses a preemptive round-robin scheduler and was booted and debugged with a cross-compiled RV32 toolchain.

Yaseen designed a parameterized FIFO in Verilog using dual-port M9K memory blocks on the DE10-Lite FPGA. Read and write modules operated at different clock frequencies to demonstrate clock-domain crossing data transfer. The implementation uses a circular FIFO architecture with full and empty condition detection and was verified through ModelSim simulations and Quartus synthesis results.

Yaseen implemented Moore and Mealy finite-state-machine representations of a dice game using RTL and block schematics. He applied sequential network design through counters and memory, verified the design with Verilog testbenches and ModelSim, and demonstrated the design on the DE10-Lite FPGA.