Projects
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Yaseen built a real-time matched-filter object detector on the Terasic DE1-SoC using a D8M camera input and VGA output. The design processes a live video stream in Verilog, extracting a red-feature score from RGB pixels and feeding it through streaming line buffers and template score logic.
The detector uses generated object templates and hardware cross-correlation against stored weights. It includes full- and half-resolution matched-filter cores, per-frame best-score tracking, configurable thresholding, confidence reporting, and scale selection for the winning detection.
The project also includes Python tooling for converting object images into Verilog-ready template weights, debug artifacts such as crops, masks, heatmaps, and overlays, and testbenches for the feature extractor, stream delay engine, score tree, and detection logic. VGA debug modes expose heatmaps, threshold masks, bounding-box overlays, and confidence/threshold displays for hardware bring-up.
The detector uses generated object templates and hardware cross-correlation against stored weights. It includes full- and half-resolution matched-filter cores, per-frame best-score tracking, configurable thresholding, confidence reporting, and scale selection for the winning detection.
The project also includes Python tooling for converting object images into Verilog-ready template weights, debug artifacts such as crops, masks, heatmaps, and overlays, and testbenches for the feature extractor, stream delay engine, score tree, and detection logic. VGA debug modes expose heatmaps, threshold masks, bounding-box overlays, and confidence/threshold displays for hardware bring-up.
Technologies: Verilog, SystemVerilog, Python, Quartus, ModelSim, DE1-SoC, D8M Camera, VGA, FPGA Video Pipelines
Template overlay generated for matched-filter hardware weights
Yaseen designed a compact, synthesizable RV32I-style RISC-V core implemented in Verilog. The design contains a program counter, register file, ALU, control unit, and synchronous instruction/data memories designed to infer Intel M9K BRAMs.
Verification used directed testbenches, waveform inspection, ModelSim, and Verilator. An OpenLane flow generated a GDS II layout, demonstrating an end-to-end path from RTL to a fabrication-oriented layout.
Verification used directed testbenches, waveform inspection, ModelSim, and Verilator. An OpenLane flow generated a GDS II layout, demonstrating an end-to-end path from RTL to a fabrication-oriented layout.
Technologies: Verilog, RISC-V, ModelSim, Verilator, Quartus, OpenLane
RV32I-style core: RTL to FPGA to OpenLane GDS
Yaseen implemented a minimal but functional RISC-V RV32 microkernel that boots in machine mode on QEMU's virt platform. The kernel includes hand-written entry and trap assembly, timer interrupts, context switching, kernel threads with dedicated stacks, and semaphore-based synchronization.
The project demonstrates low-level platform work across C, RISC-V assembly, preemptive round-robin scheduling, and debugging with a cross-compiled RV32 toolchain.
The project demonstrates low-level platform work across C, RISC-V assembly, preemptive round-robin scheduling, and debugging with a cross-compiled RV32 toolchain.
Technologies: RISC-V Assembly, C, QEMU, Machine-mode, Trap Handling, Scheduling
RV32 Microkernel: machine-mode boot, scheduler, and virtual memory
Hardware FIFO Design
Yaseen designed a parameterized FIFO in Verilog using dual-port M9K memory blocks on the DE10-Lite FPGA. Read and write modules operated at different clock frequencies to demonstrate clock-domain crossing data transfer.
The implementation uses a circular FIFO architecture with full and empty condition detection and was verified through ModelSim simulations and Quartus synthesis results.
The implementation uses a circular FIFO architecture with full and empty condition detection and was verified through ModelSim simulations and Quartus synthesis results.
Technologies: Verilog, ModelSim, Quartus, DE10-Lite, M9K Memory, Clock Domain Crossing
Parameterized FIFO with dual-port M9K memory and clock-domain crossing
Yaseen maintains a ZMK configuration for a Planck Rev6 keyboard. The keymap defines default, lower, raise, and mouse layers with media controls, bootloader/reset bindings, scroll controls, and pointer movement.
The repository includes a GitHub Actions build matrix for the Planck target and is mostly a fun side project for personal keyboard bindings.
The repository includes a GitHub Actions build matrix for the Planck target and is mostly a fun side project for personal keyboard bindings.
Technologies: ZMK, Zephyr, Device Tree, Keyboard Firmware, GitHub Actions
FPGA Dice Game
Yaseen implemented Moore and Mealy finite-state-machine representations of a dice game using RTL and block schematics. He applied sequential network design through counters and memory, verified the design with Verilog testbenches and ModelSim, and demonstrated the design on the DE10-Lite FPGA.
Technologies: Verilog, ModelSim, Quartus, DE10-Lite, FSM Design
Schematic of Score Processing and Display Circuit
Built during AgentHacks with teammates, dExtra Tools extends the Dex browser agent by adding a Working Memory system, a Planning Agent, and a Frontend-WebSocket bridge for selected-text context. The system integrates with an MCP backend and enables deeper, real-time browser interaction for agent workflows. The project won Dex Best Browser Agent at AgentHacks.
Technologies: Browser Agents, MCP, WebSocket, TypeScript, AgentHacks